Latches and flip-flops are widely used in all types of electronic devices for counting, sampling, and storage of data. There are a number of different types of flip-flops named after their primary function, such as D-type flip-flops (data), J-K flip-flops (J and K inputs), and R-S flip-flops (having R and S latches, standard for “reset” and “set”) D flip-flops are clocked flip-flops having one clock pulse delay for its output.
Conventional flip-flops, such as D-type, can be used to detect the logic state of an asynchronous digital signal with timing relative to the clock signal that is non-periodic.
However, the operating conditions of the flip-flops can be violated because hold times and setup times are not always consistent with the specifications (such as provided in the data sheets) of the flip-flops used. The violation of the operating conditions of the flip-flops can cause them to go into an unstable (metastable) state that can affect the entire operation of the linked systems. Metastability can occur when both inputs to a latch are set at a logic high (11) and are subsequently set at a logic low (00). Metastability can cause the latch outputs to oscillate unpredictably in a statistically known manner. Such metastable values are then detected by other circuitry as different logic states.
It has been found that intentionally inducing metastability provides the ability to harness the unpredictability of metastable flip-flops outputs as a random number generator.
For example, as shown in FIG. 1, a latch is realized with cross connected NAND gates 115,120. The flip-flop 110 drives this latch, It receives its clock input from clock oscillator 105 through the clock input 106 of flip-flop 110, and the inverting output −Q is connected to the D input, which shapes the clock signal to square-wave. The Q output 107 is connected to both of the NAND gates 115, 120 via delay devices, 112, 114, respectively. If the two NAND gates 115, 120 were truly identical, there would be no need for the delay devices to achieve the highest probability to get the flip-flop formed by the NAND gates 115, 120 to become metastable. However, the NAND gates will ordinarily differ somewhat, and their speed difference will influence the number of times metastability occurs in a time interval.
In VLS integrated circuits there have been attempts at tunable delay by using single tapped-buffer chains, but their implementation has not been practical. The delay resolution has been too course for the dynamic fine tuning required to achieve the highest frequencies at which metastability occurs. Delays were also designed by the introduction of long wires of various lengths, which increased design expense and has been found to be difficult to control using automatic layout tools and standard element libraries.
Current designs of physical (true) random number generators based on flip-flop metastability use single tapped-buffer-chain fixed delay values between their inputs to violate setup and hold timings, in order to provoke metastability. Eventually, the metastable state resolves to some logic level, which is effectively random, depending on the internal noise of the flip-flops. However, the fixed delay values used by the prior art can cause the random number generator to be susceptible to environmental changes. In addition, fixed delay values at large manufacturing variations can make the circuit not work at all or not work at optimal speed.